Forming dielectric layers on a substrate by chemical reaction of gases is one of the primary steps in the fabrication of modern semiconductor devices. These deposition processes include chemical vapor deposition (CVD) as well as plasma enhanced chemical vapor deposition (PECVD), which uses plasma in combination with traditional CVD techniques. CVD and PECVD dielectric layers can be used as different layers in semiconductor devices. For example, the dielectric layers may be used as intermetal dielectric layers between conductive lines or interconnects in a device. Alternatively, the dielectric layers may be used as barrier layers, etch stops, or spacers, as well as other layers.
Dielectric layers that are used for applications such as barrier layers and spacers are typically deposited over features, e.g., horizontal interconnects for subsequently formed lines, vertical interconnects (vias), gate stacks, etc., in a patterned substrate. Preferably, the deposition provides a conformal layer. However, it is often difficult to achieve conformal deposition as the barrier layer formed over a feature may have surface defects including uneven thickness. During deposition, the barrier layer material may overloaf, that is, deposit excess material on the shoulders of a via and deposit too little material in the base of the via, forming a shape that looks like the side of a loaf of bread. In extreme cases, the shoulders of a via may merge to form a joined, sealed surface across the top of the via. The film thickness non-uniformity across the wafer can negatively impact the drive current improvement from one device to another. Modulating the process parameters alone does not significantly improve the step coverage and pattern loading problems.
Deposition of conformal layers over gate stacks to provide layers that are subsequently etched to form spacers is also challenging. While methods of depositing silicon nitride and silicon oxide layers for spacers using high temperature, low pressure conventional CVD have been developed, the thermal budget for such techniques is becoming too high as semiconductor device geometry continues to shrink. PECVD processes of silicon nitride and silicon oxide deposition can be performed at lower temperatures, but the step coverage and pattern loading results are not as desirable as those obtained with high temperature, low pressure CVD.
Therefore, a need exists for more conformal methods of depositing dielectric films over features in a patterned substrate.